Generally, scan/scan enable D flip-flops are widely used integrated circuits in the semiconductor industry. One use of these flip-flops may be for testing devices in a semiconductor chip. For example, the scan/scan enable D flip-flop may receive a scan input so as to test a logic circuit in the chip.
Scan/scan enable D flip-flops generally have a circuit interposed on data signal paths for selectively choosing which signal is input into the flip-flop. For example, a multiplexer may be present in the data path to selectively output a data signal, a feedback signal, or a scan input signal. However, such a circuit may cause a latency delay in the output of the circuit, which is input into the flip-flop master-slave circuit, such that the set-up time for the chosen signal is generally larger than necessary if such circuit was not present. A large set-up time may cause difficulty in the design of the integrate circuit because synchronization of appropriate signals may be difficult. Further, a large set-up time may degrade the scan/scan enable D flip-flop's performance and, thereby, degrade the standard cell library.
A smaller set-up time may make chip design simpler because a designer would not need to create a delay in some signals to synchronize the signals input into a scan/scan enable D flip-flop. Accordingly, there is a need in the art for a scan/scan enable flip-flop with a smaller set-up time to decrease complexity in integrated circuit design and to improve performance.